The present invention relates to a semiconductor device and a method for fabricating the same.
One scaling technique that has been proposed to increase the density of integrated circuit devices is to use multi-gate transistors. In these multi-gate transistors, a fin-shaped or nanowire-shaped silicon body (which are collectively referred to herein as “fins”) is formed on a substrate and a gate is formed on a surface of the silicon body.
Since multi-gate transistors have a three-dimensional (3D) channel, the use of multi-gate transistors can provide integrated circuit devices having increased integration densities. Further, current control capability can be improved even without increasing a gate length of the multi-gate transistor. In addition, a short channel effect (SCE) in which an electric potential of a channel region is affected by a drain voltage can be reduced or suppressed.